Ultrasonic coil current regulator

ABSTRACT

A control circuit for electrical contactors, starters and the like which include one or more pairs of separable main contacts is controlled by an electromagnet assembly. In order to reduce, if not eliminate, audible noise generated by the electromagnet assembly, the electrical current to the electromagnetic assembly is regulated to minimize the rate of change of magnetic flux therethrough to thereby reduce, if not eliminate, audible noise. By regulating the electrical current to the electromagnet assembly, the power consumption of the electromagnet assembly is reduced which, in turn, reduces undesirable heating of a solenoid coil within the electromagnet assembly.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to patent application Ser. No. 08/073,636,filed on Jun. 8, 1993, now U.S. Pat. No. 5,325,315 issued on Jun. 28,1994, which is a continuation of patent application Ser. No. 07/636,000,filed on Dec. 28, 1990, entitled, A PROCESS FOR AUTOCALIBRATION OF AMICROPROCESSOR BASED OVERCURRENT DEVICE AND APPARATUS, by Joseph C.Engel, Gary F. Saletta, Marlan L. Winter and Edward C. Prather,Westinghouse Case No. WE-56,158.

This patent application generally relates to electrical contactors andstarters. U.S. Pat. No. 5,168,418 filed on Apr. 19, 1991, issued on Dec.1, 1992 entitled, DOUBLE DC COIL TIMING CIRCUIT, by Rick Hurley and MarkInnes also relates to electrical contactors.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electrical contactors, electricalstarters, motor controllers and like devices which include anelectromagnetic assembly and one or more poles for connecting a sourceof electrical power to an electrical load, such as an electrical motorand more particularly to a control circuit for controlling theelectrical current applied to a coil in the electromagnetic assemblywhich automatically compensates for magnetic coupling from the mainpoles while eliminating audible noise and providing a relatively higherhold in force than known devices.

2. Description of the Prior Art

Various electrical devices are known in the art for controllingelectrical equipment, such as motors and the like. These devices includestarters, combination starters, contactors, motor controllers and thelike for controlling both single phase and multiple phase electricalequipment in reversing as well as non-reversing applications. Suchdevices include one or more pairs of separable main contacts disposedbetween such electrical equipment and a source of electrical power. Insuch devices, the separable main contacts are mechanically interlockedwith an armature that is controlled by an electromagnetic assembly. Inknown devices, one or more biasing springs, are generally used tomaintain the separable main contacts in a normally open position. Inorder to close the separable main contacts, sufficient force must begenerated by the electromagnetic assembly in order to overcome thecompression force of the biasing springs. Moreover, once the separablemain contacts are closed, it is necessary to provide sufficientelectrical power to the electromagnet assembly to overcome thecompression force of the biasing springs when the separable maincontacts are to remain in such a closed position.

In known electromagnetic contactors, such as the electromagneticcontactor disclosed in U.S. Pat. No. 4,893,102, assigned to the sameassignee as the assignee of the present invention, the electricalvoltage and electrical current to the coil in the electromagnet assemblyare controlled to overcome the compression force of the biasing springsboth during a closing operation of the separable main contacts as wellas to maintain the separable main contacts in a closed position. Morespecifically, FIG. 6 of the aforementioned U.S. patent illustrates theelectrical voltage and electrical current profiles utilized in order toclose the separable main contacts as well as maintain the separable maincontacts in a closed position. As described in detail in theaforementioned U.S. patent, the electrical voltage and current profilesare determined as a function of the force required to overcome thecompression force of the biasing springs during the various stages of aclosing stroke. As illustrated in FIG. 6 of the aforementioned U.S.patent, a full wave rectified but unfiltered source of alternatingcurrent (AC) voltage is applied to the coil. The electrical currentapplied to the coil is controlled such that the electrical powerdeveloped by the electromagnet assembly in the various stages of theclosing stroke is controlled to overcome the compression force of thebiasing springs. Thus, as shown in FIG. 6 of the aforementioned patent,an electrical current profile consisting of a plurality of electricalcurrent pulses is applied to the coil in the electromagnet assembly. Theamplitudes of the peaks of the pulses of the electrical current profileare controlled during each stage of the closing stroke in order toprovide a force, greater than the compression force of the biasingsprings. More specifically, the amplitudes of the electrical currentpulses are controlled by controlling the phase angle of the electricalcurrent applied to the coil in the electromagnet by way of a triac andmicroprocessor as described in detail in the aforementioned U.S. patent.As shown in FIG. 6 of the aforementioned patent, an electrical currentpulse is applied to the coil once each half cycle during the closingstroke and indefinitely thereafter for as long as the separable maincontacts are to remain closed in order to overcome the compression forceof the biasing springs during such a condition.

There are several problems associated with the control system describedin detail in the aforementioned U.S. patent. First, the relatively slowupdate rate of the electrical current pulses applied to the coil in theelectromagnet assembly can result in audible noise of the electromagnetassembly. More specifically, as previously mentioned, the current pulsesare updated every half cycle. Consequently, such a pulse rate can causea relatively high rate of change of magnetic flux within the coil whichresults in audible noise. Second, such a relatively slow update ratecould result in the main contacts opening as a result of magneticcoupling from the poles. More specifically, when the electricalcontactor is in a closed position the electrical current flowing throughthe poles generates a magnetic field. Due to the proximity of the polesto the electromagnet assembly, the magnetic field generated in the polesis coupled to the coil in the electromagnetic assembly by transformeraction. Since the force required to open the contacts is determined bythe lowest decay point of the electrical current in the coil betweenupdates and since the updates are so far apart, the compression force ofthe biasing springs between updates could cause the contacts to open asa result of relatively large amounts of magnetic coupling from the polesbetween updates. Another problem with the control circuit described inthe aforementioned patent is that because of the relatively low updaterate, a relatively large amount of electrical power must be supplied tothe coil in order to maintain the contacts in a closed position. Thispower causes coil heating, which is undesirable.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve the problemsassociated with the prior art.

It is another object of the present invention to provide a controlcircuit for electrical contactors and the like for providing a regulatedelectrical current to the coil such that no audible noise is emittedfrom the electromagnet assembly.

It is another object of the present invention to provide a controlcircuit for electrical contactors and the like which compensates formagnetic coupling from the main poles.

It is another object of the present invention to reduce coil heating inthe electromagnet assembly.

It is yet another object of the present invention to provide a controlcircuit which prevents the separable main contacts for opening as aresult of magnetic coupling from the main poles.

Briefly, the present invention relates to a control circuit forelectrical contactors, starters and the like which include one or morepairs of separable main contacts controlled by an electromagnetassembly. In order to reduce, if not eliminate, audible noise generatedby the electromagnet assembly, the electrical current to theelectromagnetic assembly is regulated to minimize the rate of change ofmagnetic flux therethrough to thereby reduce, if not eliminate, audiblenoise. The circuitry is also adapted to compensate for alternatingcurrent (AC) magnetic coupling from the main poles in order to provide arelatively larger hold in force when the contacts are to remain in aclosed position. By regulating the electrical current to theelectromagnet assembly, the power consumption of the electromagnetassembly is reduced which, in turn, reduces undesirable heating of asolenoid coil within the electromagnet assembly. The control circuitincludes plurality power switches adapted to be serially coupled to thesolenoid coil within the electromagnet assembly. The power switches areunder the control of a drive circuit, a trigger circuit and a timingcircuit. The drive circuit in cooperation with the timing circuit allowsthe electrical current flowing through the solenoid coil to rise to apredetermined level. After the electrical current reaches thepredetermined level, the trigger circuit triggers the timing circuit inorder to disable the drive circuit for a predetermined time period toallow electrical current through the solenoid coil to decay. After thetime period has timed out, the timing circuit enables the drive circuitto allow the electrical current through the solenoid coil to build up tothe predetermined level. Once the electrical current in the coil reachesa predetermined level, the cycle is repeated.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention, reference is made to thepreferred embodiment thereof, shown in the accompanying drawings inwhich:

FIG. 1 shows a front elevation of an electromagnetic contactor or motorcontrol apparatus with a communications module affixed to the topthereof;

FIG. 2 shows a front elevation in the same orientation as FIG. 1 of themotor control apparatus or contactor with arc box, magnetic subassembly,and crossbar subassembly omitted;

FIG. 3 shows a side elevation cut away along plane III--III of FIG. 1,of the microprocessor controlled circuit board assembly;

FIG. 4 shows a top view of the apparatus of FIG. 1;

FIG. 5 shows a partially broken away front elevation of the apparatus ofFIG. 1, with the communications module in an alternative arrangement onthe bottom of the assembly;

FIG. 6 shows a top view of the component layout of the microprocessorcontrolled circuit board assembly utilized in the apparatus of thepreceding figures;

FIG. 7 shows a front view of the circuit board assembly of FIG. 6;

FIG. 8 shows a side view of the circuit board assembly of FIGS. 6 and 7;

FIG. 9 shows a layout view of the circuit board of the communicationmodule in FIGS. 1 and 5;

FIGS. 10A-10C show a circuit schematic diagram of the circuit boardassembly shown in FIGS. 3, 6, 7 and 8;

FIG. 10D is a graph of the voltage and current waveforms developed bythe ultrasonic coil current regulator illustrating the current waveformgreatly exaggerated in accordance with an alternate embodiment of thepresent invention;

FIGS. 10E-10G are schematic diagrams of the ultrasonic coil currentregulator in accordance with the present invention;

FIG. 10H is a partial schematic diagram of an alternate embodiment ofthe ultrasonic coil current regulator illustrated in FIGS. 10E-10F;

FIGS. 11A-11D show a circuit schematic diagram of the communicationmodules shown in FIGS. 1, 5 and 9; and

FIG. 12 shows a plot of input vs. output (or derived) current.

FIGS. 13A-13C shows plots of power supply voltage at various locationsfor the power supply 202 of the communications module 200.

FIG. 14 shows a flow chart for reading circuit variables.

FIG. 15 shows a flow chart for calibrating the contactor.

DETAILED DESCRIPTION

Referring now to the drawings and FIGS. 1-5, in particular, anelectromagnetic contactor or motor controller 10 is depicted. Thecontactor or motor controller may be of the type depicted in U.S. Pat.No. 4,893,102 issued Jan. 9, 1990, to J. A. Bauer, and entitled:ELECTROMAGNETIC CONTACTOR WITH ENERGY BALANCED CLOSING SYSTEM. U.S. Pat.No. 4,893,102 is incorporated by reference herein. It should beunderstood with respect to the embodiments incorporated by referencefrom U.S. Pat. No. 4,893,102 that the physical arrangement of thecontrol circuit board as shown best in FIGS. 8, 9 and 10 thereof may bedifferent than the circuit board arrangements depicted herein. Althoughthe description of the operation of the contactor or motor controlsystem is extensively explained in U.S. Pat. No. 4,893,102, it will bebriefly outlined herein in a less detailed form. Contactor 10 is a typeof device that acts in the presence of a predetermined value of an inputelectrical variable such as line or phase current to perform a functionsuch as closing contacts to start a motor or stop a motor.

Referring specifically to FIG. 3, the contactor arrangement of thepresent invention is depicted with reference symbols referring to likeor similar elements in the contactor of FIG. 2 of theincorporated-by-reference U.S. Pat. No. 4,893,102. In particular, thereis provided a contactor or motor control apparatus 10 having aninsulating housing 12. There are a pair of spaced-apart load terminals14, 16 suitable for interconnection with an electrical load such as amotor winding which is to be controlled by the contactor or motorcontrol device 10. Load terminal 14 is interconnected with internalconductor 20 and load terminal 16 is interconnected with internalconductor 24. Internal conductor 20 is interconnected with a fixedcontact 22 and internal conductor 24 is interconnected with a fixedcontact 26. There is provided a contact carrier 42 upon which isdisposed an electrically conducting contact bridge 44 having movablecontacts 48, 46 at either end thereof which are complementary with fixedcontacts 26, 22, respectively. The contact carrier 42 is movable incontrolled relationship such that the contact bridge 44 which is affixedthereto and movable therewith causes the contacts 48, 46 to abut againstcontacts 26, 22, respectively, when there is a need or desire to closethe circuit between terminals 14, 16. In a like manner, internaloperations of the contactor or motor controller 10 is such that thecontacts 48, 46 may separate from contacts 26, 22, respectively, andremain in a disposition of separation as a function of carrier 42 movingin a different direction and causing the rigidly affixed bridge member44 to move correspondingly. Generally, as is described inincorporated-by-reference U.S. Pat. No. 4,893,102, the movement ofcarrier 42 and concurrent movement of the bridging member 44 iscontrolled by a control card or control board 128 which may include amicroprocessor as a control element. Generally, when the magnitude ofelectrical current flowing between terminals 14, 16, when the contactor10 is in a closed disposition, is appropriate, the control board 128,upon sensing that current will cause appropriate action to take placewith regard to component magnetic structures, electromagnetic solenoidstructures (such as COIL SC), and various aligned springs, to cause thecontacts 48, 46 to separate from contacts 26, 22, respectively.Furthermore, the contacts may be opened or closed manually or they maybe closed in response to electromagnetic interaction in a mannerdescribed, for example, in the incorporated-by-reference U.S. Pat. No.4,893,102. The general operation of the circuit board 128 of the presentinvention is such that it may operate similarly to the circuit boardarrangement 128 shown and described in the incorporated-by-referenceU.S. Pat. No. 4,893,102. In the present invention, apparatus and processfor calibrating the circuit board 128 is described hereinafter.

Referring specifically to FIG. 1, the front elevation of the apparatusshown in section and described previously with respect to FIG. 3, isdepicted. In particular, there is provided an opening or orifice 52 inwhich a guiding or bridging member 54 is affixed in order tolongitudinally and radially align the movable carrier 42. The frontpanel FP of the contactor 10 contains three orifices or openings throughwhich important construction features portions or parts of the circuitboard arrangement 128 are accessible. These portions or parts are aswitch CSW2, connector CJ1, and switch CSW3. The construction, operationand function, of the accessible elements will be described hereinafter.At the top portion 12T of the contactor 10 is disposed in detachablyattached a communication module 200, the construction, operation andpurpose of which will be described hereinafter.

Referring now to FIG. 2, the contactor arrangement shown in FIG. 1 isdepicted in similar orientation except that the front panel FP,including that which is called the "arc box", as well as the magneticsubassembly and the crossbar assembly have been omitted or removed. Inparticular, the arrangement of the circuit control card 128 within thecontactor internal portion is once again depicted. The arrangement ofelements CSW2, CJ1 and CSW3 is clearly shown.

Referring to FIG. 4, a top view of the contactor 10 is shown. Inparticular, the arrangement of the three-phase load terminals 16 isclearly set forth.

In FIG. 5 another embodiment of the invention is shown in which thecommunication module 200 is detachably attached to the contactor 10 atthe bottom 12B thereof.

CONSTRUCTION FEATURES OF THE CONTROL CIRCUIT BOARD 128

Referring now to FIGS. 6-8 and 10A-10C, the construction features of thecontrol board 128 are described. As shown best in FIG. 10A, there isprovided an input connector CJ1 having terminals 1, 2, 3, 4. Terminal 4is connected to system common or ground (hereinafter "ground"). One sideeach of resistive elements CR28, CR29, CR34, CR35 are also connected toground. Terminal 4 is designated "C". Terminal 1 is connected to oneside of a resistive element CR1 to one side each of resistive elementsCR28, CR34 and to an output designated "3". Terminal 2 is connected toone side of a resistive element CR2, to a terminal "P", and to one sideeach of resistive elements CR29, CR35. Terminal 3 is connected to oneside of a resistive element CR3, to a terminal "E" and to one side of avaristor element CMV1. Terminal "E" may have impressed thereupon acontrol voltage to ground. In one embodiment of the invention that valuemay be 120V AC. The other side of resistive element CR1 is connected toone side of capacitive element CC1, and to terminal CP2 and terminal PC1of an integrated circuit chip CU1. The construction and operation ofchip CU1 will be described hereinafter. The other side of resistiveelement CR2 is connected to one side of a capacitive element CC2 and toterminal CP1 and terminal PC0 of chip CU1. The other side of resistiveelement CR3 is connected to one side of a capacitive element CC3 and toterminal CPO of chip CU1. The other side of the varistor CMV1 andcapacitive elements CC1, CC2, CC3 are connected to ground. Thethree-phase sensors designated CL1A, CL1B and CL1C are connected at oneside each thereof to ground and to one side each of resistive elementsCR6, CR5 and CR4, respectively. The other side of resistive elementsCR4, CR5, CR6 are connected to input terminals MUX2, MUX1, MUX0respectively of chip CU1. The latter inputs are designated "PHASE3","PHASE 2" and "PHASE 1", respectively. The foregoing represents thecurrent sensing arrangement for the system.

Referring now to FIGS. 10B and 10C, there is shown an input connectorCJ2 which is externally interconnectable with the communication module200, in a manner to be described hereinafter. Terminal 7 of connectorCJ2, designated "RR", is connected to one side of a resistive elementCR20 and one side of a resistive element CR32. The other side ofresistive element CR32 is connected to ground. The other side ofresistive element CR20 is designated "REMOTE RESET SENSE" and isconnected to the CP3 terminal of the chip CU1. Terminal 6 of connectorCJ2 is designated "R" and is connected to one side of a resistive CR21,the other side of which is connected to terminal PC6 of chip CU1. Thisis designated the "LEDOUT" terminal. Chip CU1 may be of the type knownas a SURECHIP which is a proprietary device of the Westinghouse ElectricCorporation. The SURECHIP will be described in detail hereinafter.Terminal 2 of connector CJ2 is designated "CC" and is connected toground. Terminal 1 of connector CJ2 is designated "VAC" and is connectedto the "E" control voltage as described previously. Terminal 5 ofconnector CJ2 is designated "DO" for data out and is connected to theoutput terminal SDO of the chip CU1. Terminal 4 of connector CJ2 isdesignated "DI" for data in and is connected to one side of a resistiveelement CR24, one side of capacitive elements CC13, and to the inputterminal SD1 of the chip CU1. The other side of resistive element CR24and the other side of capacitive element CC13 are connected to ground.Terminal 3 of the connector CJ2 is designated "CLK" for clock isconnected to one side of resistive element CR33, one side of acapacitive element CC5, and to the SCK terminal of the chip CU1. Thisterminal is designated "COMMUNICATIONS SLAVE". The other side ofresistive element CR33 and the other side of capacitor element CC5 areconnected to ground.

The terminal PC7 of the chip CU1 is connected to one side of a resistiveelement CR22 and one side of the switch CSW3. The other side of theswitch CSW3 is connected to ground. The other side of resistive elementCR22 is interconnected to have impressed thereupon voltage CVDD, thesupply of which will be described hereinafter. Switch CSW3 is a normallyopen push-button switch. Terminals PA0 through PA7 of chip CU1 areconnected to separate terminals of the programming switch CSW2. Each ofthe terminals PA1 through PA7 is connected to one side of an appropriateresistive elements CR37 through CR43. The other side of resistiveelements CR37 through CR43, respectively, is connected to voltage sourceCVDD. Terminal AGND and terminal BSEN of chip CU1 is connected toground.

Capacitive element CC12 is connected at one side thereof to ground. Theother side capacitive element CC12 is connected to terminal MUX4 of thechip CU1, and to one side of a resistive element CR7. The other side ofresistive element CR7 is connected to the anode of a diode CCR12 and thecathode of a diode CCR13, as well as one side of a resistive elementCR17, the other side of which is connected to ground. The anode of diodeCCR13 is connected to the anode of a diode CCR11, to the anode of azener diode CCR5, to one side of a resistive element CR16, and to thedrain terminal of a field effects transistor CQ4. The cathode of thediode CCR12 is connected to the cathode of a diode CCR10, to one side ofa resistive element CR15, to the cathode of a diode CCR4 to thecollector of a transistor CQ3, and to terminal 1 of a connector CJ3.Connector J3 is interconnected to one side of a solenoid coil COIL SC inthe contactor 10 for control of the armature member or carrier 42 in amanner described previously with respect to theincorporated-by-reference U.S. Pat. No. 4,893,102. The other side of thecoil COIL SC is connected to terminal 2 of the connector CJ3. Terminal 7of connector CJ3 is connected to the source terminal of the fieldeffects transistor CQ4, and to the anode of diode CCR4. The other sideof the resistive element CR15 is connected to the anode of zener diodeelement CCR5. The junction point between the resistive element CR15 andthe anode of zener diode CCR5 is connected to the collector terminal ofan output transistor of a chip CU2. The emitter terminal of thetransistor of chip CU2 is connected to one side of a resistive elementCR18, one side of a resistive element CR14, the base of transistor CQ3.The emitter of transistor CQ3 is connected to the gate terminal of thefield effect transistor CQ4, to the other side of the resistive elementCR14, and to the other side of the resistive element CR16. The otherside of resistive element CR18 is connected to the base of thetransistor element of the chip CU2. The input circuit for the chip CU2comprises a light-emitting diode, the anode of which is connected to oneside of a resistive element CR26 and the cathode of which is connectedto the system common or ground. The other side of the resistive elementCR26 is connected to receive the signal "FET DRIVE" from the chip CU1.The chip CU2 represents a diode-driven transistor output isolatingdevice comprising a light-emitting diode as the input and alight-receptive transistor as the output. It essentially acts as anisolation device.

The anode of the diode CCR10 and the cathode of the diode CCR11 areconnected together and to one side of a resistive element CR44, one sideof a capacitive element CC8, one side of a resistive element CR8, and tothe control voltage "E". The other side of the resistive element CR44and the other side of the capacitive element CC8 are connected to oneside of a resistive element CR12 and one side of a resistive elementCR46. The other side of resistive element CR12 and the other side ofresistive element CR46 are interconnected together, and the anode of adiode element CCR2 and regulating terminal of a zener diode CCR1 thecathode of which is connected to ground The other side of resistiveelement CR8 is connected to the anode of a diode element CCR6, thecathode of which is connected to one of a resistive element CR9 and tothe MUX3 terminal of the chip CU1. The cathode of the diode CCR2 isconnected to the collector of a transistor CQ1, one side of a resistiveelement CR47, one side of a capacitive element CC10, and one side of aresistive element CR13. The other side of resistive element CR13 isconnected to one side of a capacitive element CC14, the VA terminal ofthe chip CU1, and to the base of transistor CQ1. The other side ofresistive element CR9 is connected to one side of a capacitive elementCC6, one side of a resistive element CR10, the other side of capacitiveelement CC14, and ground. The other side of capacitive element CC6 isconnected to the MX0 terminal of the chip CU1 which internally isconnected to an A-to-D converter designated "A/D". The other side ofresistive element CR10 is connected to one side of a resistive elementCR11 and to the VADJ terminal of the chip CU1. The other side ofresistive element CR11 is connected to the VREF terminal of the chipCU1. The terminal PD6 of the chip CU1 is designated "LINE MIMIC". Theterminal PD7 of the chip CU1 is interconnected with ground and the GNDterminal of the chip CU1. The VDD terminal of the chip CU1 is connectedto provide the power supply voltage VDD as described previously and isconnected to the emitter of previously described transistor CQ1, oneside of capacitor CC4, one side of resistive element CR27, and to theIRQ terminal of chip CU1. The other side of capacitive element CC4 isconnected to ground. The other side of resistive element CR27 isconnected to one side of a capacitive element CC7, to the RESN terminalof the chip CU1, and to one input terminal of an integrated circuit CU3.The other side of resistive element CR47 is connected to the anode of azener diode CCR3 and to another terminal for the chip CU3. The groundterminal of chip CU3, the anode of the zener diode CCR3, and the otherside of the capacitive element CC7 are connected to ground. Connectedbetween the OS2 and OS1 terminals of the chip CU1 is a resistive elementCR19.

The terminal MUX5 of the chip CU1 is connected to one side of aresistive element R36 and is designated "POWER DOWN SENSE". Terminal PC4of the chip CU1 is connected to one side of a resistive element CR30 andis designated "POWER DOWN SAVE". The other side of resistive elementCR30 is connected to the other side of resistive element CR36, to oneside of a resistive element CR31, and one side of a capacitive elementCC11. The other side of capacitive element CC11 and the other side ofresistive element CR31 are connected to ground Terminal PC2 of chip CU1is designated "NC". Terminal PC3 of chip CU1 is designated "RELAY OUT".Terminal PC5 of chip CU1 is designated FET DRIVE, and as was describedpreviously, is interconnected as an input to one side of a resistiveelement CR26.

CONSTRUCTION FEATURES OF THE COMMUNICATION MODULE 200

Referring now to FIG. 9 and FIGS. 11A-11D, there is shown a circuitboard layout and circuit schematic diagram, respectively, for thecommunication module 200, otherwise depicted in FIG. 1. Thecommunication module 200 which may be otherwise known as a smartminicomputer or PONI "PRODUCT OPERATED NETWORK INTERFACE" may act as aninterface device between a remote personal computer PC and theelectrical contactor 10, relay, etc., as the case may be. In thisembodiment of the invention there are provided three rotary switchesMSW1, MSW2, MSW3 representing the least significant address, the middleaddress, and the most significant address, respectively, for externalaccess to the device 10 from a data highway, for example. Inputs MC2,MC5 of each of the aforementioned switches are grounded. The hexadecimaloutputs "1", "2", "4", "8" for each switch, respectively, are providedto INCOM communication chip MU4 the INCOM chip is proprietary to theWestinghouse Electric Corporation and is further described in U.S. Pat.No. 4,644,547, issued Feb. 17, 1987 to L. C. Vercellotti et al. andentitled, "Digital Message Format for Two-Way Communication and ControlNetwork". U.S. Pat. No. 4,644,547 is incorporated by reference herein.In this embodiment of the invention, INCOM chip MU4 operates in theexpanded mode slave configuration. For the output of switch MSW1, the"1" output is provided to the A0 input of the chip MU4. The "2" outputis provided to the A1 input, the "4" is provided to the A2 input, andthe "8" is provided to the A3 input. In a like manner, for switch MSW2the "1", "2", "4", "8" outputs are provided to the A4, A5, A6, A7 inputsof the chip MU4. Finally, for the switch MSW3 the "1", "2", "4", "8"outputs are provided to the A8, A9, A10, A11 inputs, respectively, ofthe chip MU4. The RX input and TX output of the communication chip MU4are connected with complementary inputs and outputs of other portions ofthe communication module 200 in a manner which will be describedhereinafter. Signal MRX is provided to the RX input and signal MTX comesfrom the TX output. There is provided a capacitor element MC1 one sideof which is grounded and the other side of which is connected to theOSC1 input of the chip MU4, one side of a crystal MY1, and one side of aresistive element MR1. The other side of the crystal MY1 and the otherside of the resistive element MR1 are connected to the OSC2 input of thecommunication chip MU4 and one side of a capacitive element MC4, theother side of which is grounded. The crystal MY1 may, in one embodimentof the invention, be a 3.6864 MHz crystal. The BUSY output of thecommunication chip MU4 is connected to the PA4 input of a microprocessorMU3. Microprocessor MU3 may be a Motorola chip of the type designatedMC6805. The INT output of the communication chip MU4 is connected to thePA3 input of a microprocessor MU3. The SERDAT terminal of thecommunication chip MU4 is connected to the terminal PA2 of themicroprocessor MU3. The SCRCLK terminal of the communication chip MU4 isconnected to the PA1 terminal of the microprocessor MU3 and the R/Wterminal of the communication chip MU4 is connected to the PA0 terminalof the microprocessor MU3. The VDD terminal of the communications chipMU4 is connected to the MVDD power supply voltage from power supplymodule 202 for power and to one side of capacitive element MC3. Theother side of the capacitive element MC3 is connected to ground. Theterminal PB0 of the microprocessor MU3 is connected to one side of aresistive element MR19 and one side of a resistive element MR20. Theother side of the resistive element MR19 is connected to ground and theother side of the resistive element MR20 is connected to the MVDDvoltage. All of the following terminals in the microprocessor MU3 areconnected to ground PA7, PA6, PA5, PB3, PB4, PB5, PB6, PB7, VSS, PC7,PC6, PC5, PC4, PC3, PC2, PC1, PC0. The following terminals of themicroprocessor MU3 are connected together, to one side of a capacitiveelement MC12, and to the MVDD power supply voltage: VPP, IRQ, VDD, TCAP,PD7, SS, RD1. The RESET terminal of the microprocessor MU3 is connectedto receive a RESET signal from power supply module 202 in a manner to bedescribed hereinafter. There is provided a capacitive element MC11, oneside of which is connected to or ground, and the other side of which isconnected to one side of a crystal MY3, one side of a resistive elementMR3, and to the OSC1 terminal of the microprocessor MU3. The other sideof the crystal MY3, the other side of the resistive element MR3, and oneside of a capacitive element MC5 are connected to the OSC2 inputterminal of the microprocessor MU3. The other side of the capacitiveelement MC5 is connected to system common or ground. Terminals TCMP andTD0 of microprocessor MU3 are not externally connected. The SCK terminalof the microprocessor MU3 is connected to one side of a resistiveelement MR7. The MOSI terminal of the microprocessor MU3 is connected toone side of a resistive element MR5. The MIS0 terminal of themicroprocessor MU3 is connected to one side of a resistive element MR8and one side of a resistive element MR4, the other side of which isgrounded. The other side of the resistive elements MR5, MR7, MR8 areconnected to the DO, CLK, DI terminals of a connector MJ2.

INPUT NETWORK 201

Referring specifically to FIG. 11D, there is provided an input networkfor module 200 which includes an input port or connector MP2. Terminal 1of input connector MP2 is connected to one side of a resistive elementMR9 and one side of a capacitive element MC9. The input terminal 1 ofthe connector MP2 is designated "COMM IN". The other side of capacitiveelement MC9, and the other side of resistive element MR9 are connectedto one side of a first primary winding MP1 of a transformer MT1.Terminal 2 of connector MP2 is connected to the other terminal of thetransformer winding MP1 of the transformer MT1. Terminal 2 of connectorMP2 is designated "COMM OUT". The secondary windings of the transformerMT1 are designated MS1 and MS2. Connected in parallel across thesecondary winding MS1 are resistive element MR10 and a capacitiveelement MC10. Connected to the high side of the capacitive element MC10is a voltage MVU which is provided from a power supply which will bedescribed hereinafter. Connected to one side of the secondary windingMS2 is one side of a resistive element MR11, the other side of which isconnected to the anode of a diode MCR3. The cathode of the diode MCR3 isconnected to the other side of the transformer secondary winding MS2.Connected in parallel with a diode MCR3 is a second diode MCR4 connectedin an anode-to-cathode, cathode-to-anode relationship. Connected to theanode of the diode MCR3 is one side of a resistive element MR12 and oneside of a resistive element MR13. The other side of a resistive elementMR12 is connected to the positive input terminal of a isolatingcomparator MU1A. The negative input terminal of the comparator MU1A, theanode of the diode MCR4, and the cathode of the diode MCR3 are connectedto ground. The other side of the resistive element MR13 is connected tothe output of the comparator MU1A and to one side of a resistive elementMR15. The output of the comparator MU1A provides the MRX signal for thechip MU4 as described previously. The other side of the resistiveelement MR15 is connected to one side of a resistive element MR16, oneside of a resistive element MR18, and to voltage MVDD. The other side ofthe resistive element MR16 is connected to the positive input terminalof a comparator MU1B and to one side of a resistive element MR17. Thenegative terminal of the comparator MU1B receives the MTX output signalfrom the chip MU4 as described previously. The comparator MU1B isinterconnected with the voltage source MVU from power supply 202 andwith ground in an appropriate manner. The output of the comparator MU1Bis connected to the other side of the resistive element MR18 and to thegate of a Field Effect Transistor (FET) device MQ1. The drain of thetransistor device MQ1 is connected to ground as is the other side of theresistive element MR17. The source of the transistor device MQ1 isconnected to one side of a resistive element MR14, the other side ofwhich is connected to the cathode of a light-emitting diode MLED1, theanode of which is connected to common terminal between the previouslydescribed resistive element MR10, and capacitive element MC10.

POWER SUPPLY CIRCUIT 202

Referring specifically to FIGS. 11B and 11C, there is shown connected tothe MJ2 connector a conductor designated VAC which is provided to theanode of a diode MCR1. The cathode of the diode MCR1 is connected to oneside of a resistive element MR6, one side of a resistive element MR25,one side of a resistive element MR22, one side of a resistive elementMR23, one side of a resistive element MR24, and one side of a resistiveelement MR26. The other side of resistive element MR6 is connected toone side of a resistive element MR21, the cathode of a zener diode MCR2,the other side of resistive element MR25, and the terminal IN of a RESETMU6. RESET device MU6 and RESET device MU2 to be described hereinaftermay be Motorola devices designated MC34064. Terminal RST of RESET deviceMU6 is connected to the other side of resistive element MR22 and to thegate terminal of a transistor MQ2. Elements MR22, MR25, MCR2, MCR5, MQ2and MU6 form a voltage sensing and switching means as describedhereinafter. The drain terminal of the transistor MQ2 is connected tothe other side of the resistive element MR23, the gate terminal orcontrol of a FET MQ3, the cathode or regulating terminal of the zenerdiode MCR6, and the cathode or regulating terminal of a zener diodeMCR5. The other side of resistive elements MR24, MR26 are connectedtogether and to the drain or input terminal of the FET MQ3. The sourceor output terminal of the transistor MQ3 is connected to the anode ofthe zener diode MCR6 and the anode of a diode MCR7. The cathode of thediode MCR7 is connected to one side of a capacitive element MC6 and toprovide the output voltage MVU. There is provided a voltage regulatorMU5, the VIN input terminal of which is also connected the voltage MVU.There is a "+5" terminal for the device MU5 which is connected to oneside of a resistive element MR2 and the IN terminal of a RESET deviceMU2. This later terminal provides the voltage MVDD. The RST terminal ofthe device MU2 is connected to the other side of the resistive elementMR2, to one side of a capacitive element MC13, and to the previouslydescribed RESET terminal of the microprocessor MU3 for providing a RESETsignal thereto connected. Four terminals designated GND on the deviceMU5 are connected to ground. In a like manner, the other side ofresistive element MR21, the anode of the zener diode MCR2, the GNDterminal of the device MU6, the drain of the transistor element MQ2, theanode of the zener diode MCR5, the other side of the capacitive elementMC6, the other side of the capacitive element MC13, and the GND terminalof the device MU2 are connected to ground.

OPERATION

Referring to FIGS. 10A and 10B, explanation of the operation of thepreferred embodiment of the invention is begun. Terminal 4 otherwisedesignated "C" of connector CJ1 is internally connected to ground. Thisterminal is interconnected externally with the user's ground. Connectedto terminal 1 externally of connector CJ1 is a customer's pushbutton orsimilar initiating device which provides the output signal "3" which isindicative of a start operation. This is supplied to terminal CP2 ofchip CU1 in order to begin operation. Connected externally to terminal 2of terminal CJ1 is a "P" signal which is indicative that it is"permissible" to utilize the contactor circuit. This may be referred toas an ENABLE signal which is supplied by the user. Finally, connected toterminal 3 is the user's control voltage which, in a preferredembodiment of the invention, may be 120V AC. This latter voltage isdesignated "E". Varistor CMV1 operates in conjunction with filternetwork CR3, CC3 to provide the control signal "E". Resistors CR29, CR35operating in parallel cooperate with resistor CR2 and capacitor CC2provide the filtered signal "P". Resistive elements CR34, CR28 operatingin conjunction with resistive element CR1 and capacitive element CC1provide a filtered input for the "START" signal. The "START" signal issupplied to the chip CU1 by way of voltage divider CR1, CC1, to the CP2,PC1 inputs of the microprocessor CU1, to indicate a start operation isto begin. Enable or permission signal "P" is supplied to themicroprocessor CU1 by way of the voltage divider created by theresistive elements CR2, CC2 and provides an input signal to terminalsCP1 and PC0 of the chip CU1 to indicate that it is permissive to utilizethe chip.

With attention to FIG. 10B, a method for closing and opening thecontacts of the contactor 10 is taught. In particular there is provided,as is shown in FIG. 3 for example, the coil COIL SC for moving themember 42 for thus causing the bridging member 44 to move in such adirection as to cause the contacts 22, 26, 46, 48 to close in the mannerdescribed previously, or to open in the manner described previously,depending upon where energy is supplied to the coil COIL CS or not.Energy may be supplied to the coil COIL CS in any convenientcontrollable fashion, but in a preferred embodiment of the invention itis provided by way of interconnection with the control voltage "E" asactuated by a signal designated FETDRIVE going positive as a function ofaction within the chip CU1. The diodes CCR10, CCR11, CCR12, CCR13provide a full-wave bridge rectifier for the AC voltage "E" asinterconnected between terminal 3 and terminal 4 of connector CJ1. Thisvoltage is impressed across the combination of the resistive elementCR15 and the zener diode CCR5 to provide a controlled voltage for thecollector of the output of the transistor of the optocouple transistornetwork CU2. Normally, if the FETDRIVE signal is zero, the diode portionof the optocoupler or input circuit thereof remains unenergized, and thetransistor output allows the base of the transistor CQ3 to assume asufficient value of current and voltage to allow the base of thetransistor CQ4 to place transistor CQ4 in an open circuit dispositionbetween the collector and emitter thereof. However, if the FETDRIVEoutput signal is present, the diode of the optocoupler CU2 is energized,thus providing energizing light to the base of the transistor outputthereof, thus causing the transistor CQ3 to conduct in such a manner asto cause the transistor CQ4 to assume a short circuit dispositionbetween the emitter and collector thereof, thus providing the fullvoltage "E" between the terminals 1 and 2 of the connector CJ3 andacross the diode CCR4. This causes the coil COIL CS to conductelectrical current, thus causing the contacts of the aforementionedcontactor to close, thus providing a path for current through theaforementioned contactor.

Referring to FIGS. 10B, 10A, it will be noted that the presence of thevoltage "E" will cause the voltage divider-filter represented by theresistive element CR3, and capacitive element CC3 to provide an inputsignal to the CPO input of the chip CU1 by way of conductor LINE SENSE,thus indicating that line voltage is present and that any operationwithin the chip CU1 or outside thereof which depends upon the presenceof that voltage is allowable. In a like manner, resistive element CR17will conduct some of the current which flows through the coil COIL SCwhen the coil is energized, thus providing an input indication back byway of the COIL I SENSE line to the filter represented by resistiveelement CR7 and capacitive element CC12. The midpoint of this filterelement is interconnected with the MUX4 input terminal of the chip CU1,thus indicating that current is flowing in the coil, thus providing animplied input that the contactor contacts are closed.

Coils CL1A, CL1B, CL1C are interconnected at one end thereof to ground.These coils sense phase current flowing in phases A, B, C, or 1, 2, 3,as the case may be, of a three-phase electrical power system which isinterconnected with the contacts of the aforementioned contactor. Thesecoils provide analog current information to the chip CU1 by way of inputterminals MUX0, MUX1, MUX2 for PHASES 1, 2, 3, respectively.

In order to generate the voltage +VU1, it is necessary to take the 120Vcontrol voltage "E" and capacitively couple it to generate theappropriate voltage. Capacitor CC8 performs this function. The resistiveelement CR44 is a discharge resistor which will discharge the capacitorCC8 in the event of a loss of power. Resistive element CR12 andresistive element CR46 together act as a parallel current-limitingresistive network. Zener diode CCR1 clips the voltage to a usable valuewhich in the preferred embodiment of the invention is approximately 15V.Diode CCR2 is a half-wave rectifier and resistive element CR13 andcapacitive element CC10 act as a filter. Capacitive element CC10 is acharge filter. The voltage +VU1 is therefore generated at the junctionpoint between the resistive element CR13 and capacitive element CC10.Voltage +VU1 then cooperates with resistive element CR13 in combinationwith capacitive element CC14 and transistor CQ1 to create a 5V powersupply. This value is designated CVDD and it exists at the emitter oftransistor Q1 and is supplied to the CVDD terminal of the chip CU1.Voltage CVDD cooperates with capacitive element CC4 and resistiveelement CR27 to create a RESET network. This RESET network cooperateswith the RESN input terminal of the chip CU1. If the voltage VDD becomesnoisy, thus creating a possibility that the chip CU1 will operate in anerratic manner, the RESET network will reset the chip CU1 at terminalRESN. Element CU3 is part of an undervoltage reset. If the voltage CVDDis above 4.5V, it will operate to pull the voltage up toward 5V at thetop of capacitive element CC7. If voltage VDD is below 4.5V, the chipCU1 will be reset by way of the reset network RESN. Zener diode CCR3protects the input to the regulator circuit CU3 so that the voltageimpressed thereacross does not get larger than a predetermined valuewhich, in a one embodiment of the invention, is about 5.6V. Resistiveelement CR19 which is interconnected with terminals OS1, OS2 of the chipCU1 sets the frequency at which chip CU1 oscillates. Resistive elementsCR10, CR11 form a trim circuit which is utilized to set the VADJ (Vadjust) and VREF (V reference) capabilities of the chip CU1. In oneembodiment of the invention, resistive elements CR10, CR11 are notadjustable.

Referring now to FIG. 10C, the power-down circuit will be described. Anamount of electrical charge is stored in capacitive element CC1 that isin proportion to the amount of heat in the motor controlled by thecontactor or motor control device 10. There is stored internally in thechip CU1 a model for what the heat of the motor will be as a function ofinput variables such as motor current. The electrical charge is suppliedby way of terminal PC4. There is also provided a POWER DOWN SENSE linewhich is connected to terminal MUX5 of chip CU1. It utilizes the voltageon capacitor C11 to decide how hot the motor was when power was lost.There is also provided a REMOTE RESET SENSE line in which resistiveelement CR20 and resistive element CR32 cooperate with the RR signal onterminal 7 of connector CJ2. These, in conjunction with resistiveelement R21, can provide a remote electrical reset and indication.Switch element CSW3 is a reset switch. When the contactor 10 has beentripped and switch CSW3 is actuated, the entire unit will be reset andbe prepared to run again. Capacitive element CC13 and resistive elementCR24 act as a noise filter for the communications channel or terminaldesignated DI. Likewise, resistive elements CR23, CR33 and capacitiveelement CC5 act as a noise filter for the clock channel CLK. Switch CSW2in conjunction with its various terminals and the associated pulldownresistive resistors CR37 through CR43 is an option setting switch,whereby the user can throw certain parts of the switch to indicateheater settings, motor size, etc for programming chip CU1.

Referring now to FIGS. 11A-11D, the operation of the communicationsmodule 200 will be described. In particular, there is provided aconnector MP2 which represents the first stage of the input network 201for the communications device 200. Connector MP2 is interconnectablewith a communications interface CONI "computer operated networkinterface" in a remote personal computer PC in a manner which willdescribed hereinafter. Terminal 1 of connector MP2 interconnects withthe line designated COMM IN which feeds through the capacitive elementMC9 and a resistive element MR9, which operate as a filter. There isprovided transformer MT1 having the one side of the primary winding MP1thereof connected to COMM IN line and the other side thereof connectedto the COMM OUT line which, in turn, is connected to terminal 1 ofconnector MP2. The pair of secondaries MS1, MS2 for transformer CT1interact with the remaining part of the communications module 200.Resistive element MR11 is a current-limiting element and diodes MCR3,MCR4 are clipping diodes. The result of the action of the clippingdiodes MCR3, MCR4 is to take the AC signal which is provided by thesecondary winding MS2 of the transformer MT1 and clip the voltage tonear zero in both the positive and negative direction. Resistive elementMR12 feeds the positive terminal of the comparator MU1A, the negativeterminal of which is grounded. The output terminal of the comparatorMU1A provides the output signal MRX. Comparator MU1A basically operatesas a squaring device, which ensures that the signal MRX has anacceptable square wave shape. Resistive element MR13 provides hysteresisfor the comparator MU1A so that it does not oscillate about a singlevalue. Resistive element MR15 is a pull-up resistor; that is because theoutput of the comparator MU1A is of the open collector variety. There isalso provided a similar comparator MU1B which has available to thenegative terminal thereof the signal MTX, which will be described morefully hereinafter. Signal MTX is either a 5V or a 0V signal. Resistiveelements MR16, MR17 are bias resistors which place a bias ofapproximately 2.5V on the positive terminal of the comparator MU1B.Resistive element MR18 is a pull-up resistor similar to resistiveelement MR15. When the output of the comparator MU1B is high or at adigital 1, the field effects transistor MQ1 is energized or turned on,thus drawing electrical current through current-limiting resistiveelement MR14, and through the light-emitting diode element MLED1.Energization of the light-emitting diode element MLED1 is an indicationto the user that the entire unit is, in fact, in a transmitting mode.Resistive element MR10 and capacitive element MC10 merely act incombination as a noise filter. Field effects transistor MQ1 is anoscillating device, and when it is turned on it provides an oscillatingAC signal which generates a signal across the transistor secondary MS1for application to the communications network represented by the linesCOMM IN and COMM OUT. This is true even though the signal MTX is anON/OFF type DC signal. Consequently, element MQ1, which may be a metaloxide FET transformer is a modulator. On the other hand, the operationof the input circuit represented by resistive element MR11, diodes MCR3,MCR4 and resistive elements MR12, MR13, MR15 and comparator MU1A act asa demodulator network.

Attention is now called to the rotary switches MSW1, MSW2, MSW3 of FIG.11A. Basically, these switches provide address information for theentire network. It does this by providing a digital code to the INCOMchip MU4. Once the INCOM chip MU4 has its address, when a signal MRX isdelivered to the INCOM chip MU4 by way of the input network 201previously described, the INCOM chip MU4 scans the address informationprovided in part of the transmission from terminal MRX and decideswhether the INCOM chip has been properly addressed or not. If the INCOMchip has been properly addressed in compliance with the addressinformation provided by the switches MSW1 through MSW3, the INCOM chipMU4 will operate to receive further information from the communicationnetwork and provide useful functions such as motor starting. Obviously,address information is provided from the switches MSW1 through MSW3 byway of the twelve lines interconnected with the input terminals A0through A11 of the INCOM chip MU4. The RX and TX terminals whichinterconnect with the MRX and MTX signals, respectively, of the inputcircuit 201 as described previously are shown on the INCOM chip MU4.INCOM chip terminals OSC1 and OSC2 are interconnected with a well-knownoscillator circuit arrangement comprising capacitive elements MC1, MC4,resistive element MR1, and crystal MY1. Capacitive element MC3 which isinterconnected between ground and the combination of the input terminalVDD and the power supply voltage CVDD is merely a bypass capacitor.Resistive elements CR19, CR20 provide a voltage divider between groundand voltage VDD. The voltage divider point of the latter network isconnected to the PBO input of the microprocessor MU3 for the purpose ofpreventing a user from effectuating commands into the microprocessorCU3, which are undesirable. It is therefore a disabler of certainmicroprocessor commands.

Referring additionally to FIG. 11B, terminals PA0 through PA4 of themicroprocessor MU3 are interconnected with the R/W, SCRCLK, SERDAT, INT,and BUSY terminals of the INCOM chip MU4, respectively. Terminals BUSYand INT provide information to the microprocessor MU3, the BUSY terminaltelling the microprocessor when not to communicate with the INCOM chipand the remainder of the communications network under certaincircumstances and the INT terminal telling the microprocessor when tocommunicate. Terminal R/W is a READ/WRITE terminal whereby the INCOMchip MU4 is alerted whether it is to write information to themicroprocessor MU3 by way of the serial data line SERDAT or to readinformation from the microprocessor MU3 by way of the serial data lineSCRDAT. The serial clock line SCRCLK is a pulsing or clocking networkfor the INCOM chip MU4 under the command of the microprocessor MU3.Basically, data provided to the INCOM chip MU4 by way of the inputterminal RX or taken from the input chip MU4 by way of the outputterminal TX is transmitted back and forth by way of this serial dataline SCRDAT to and from the microprocessor MU3. Consequently, INCOM datafrom the external personal computer PC which comes into the inputnetwork 201 by way of connector MP2 is properly demodulated and sent tothe INCOM chip MU4 by way of terminal RX, and fed from the INCOM chipMU4 to the microprocessor MU3 by way of the serial data line SERDAT.Outgoing digital information from the microprocessor MU3 traverses theserial data line SCRDAT in the opposite direction, is routed by way ofthe INCOM chip CU4 to the terminal TX, and thence to the input network201 where it is modulated and provided to the personal computer PC as anoutput by way of the connector MP2. The terminals SCK, MOSI, MISO ofmicroprocessor MU3 are interconnected to the connector MJ2 and fromthere to complementary terminals on the connector CJ2 of the electroniccircuit board 128 as described previously with respect to FIG. 10C, thecomplementary terminals being shown to the extreme right on FIG. 10C.The aforementioned connectors MJ2 and CJ2, and the lines or cablesconnected therebetween, represents the main communication path betweenthe microprocessor MU3 and the chip CU1. The clock signal which isprovided by way of terminal SCK to line CLK for terminal MJ2 is alwaysgenerated in the microprocessor MU3. Consequently, the microprocessorMU3 represents a master and the chip CU1 represents a slave as far asthe clock signal CLK is concerned. Data is transferred back and forthbetween microprocessor MU3 (master) and chip CU1 (slave) by the MOSI(master out/slave in) line, and the MISO (master in/slave out) line, orterminals of the microprocessor MU3.

POWER SUPPLY 202

Referring specifically to FIGS. 11C and 13A-13C, a pseudo switchingpower supply 202 is taught. In particular, AC power is delivered to thepower supply 202 by way of the connector MJ2 at terminals 1, 2 thereof(see FIG. 11B). The AC power is delivered between the lines VAC and CCfrom complementary lines on terminal 1 and 3 of connector CJ2. One ofthe advantages of the present invention lies in the fact that the ACvoltage applied as described may range from a very low value to as highas 200V. The AC voltage is voltage "E" as shown in FIGS. 10A and 10C.Diode element MCR1 half-wave rectifies the input voltage as shown atPoint 202A and in waveform 202A in FIG. 13A. In one embodiment of theinvention it is desirable to produce 24V as an output voltage MVU, andtherefore the 24V line is shown in FIG. 13A although that is notlimiting. In the present embodiment of the invention, resistive elementsMR6, MR21 are chosen to produce the ultimate voltage wave shape at MVUas depicted in FIG. 13C. Zener diode element MCR2 clips the voltagebetween resistive elements MR25 and MR21 at 5.6V to protect the lowvoltage reset device MU6 to thus limit the input voltage on terminal INthereof to no more than 5.6V. Resistive element MR25 is acurrent-limiting resistor. Device MU6 is a "low voltage" reset devicewhich may be of the kind designated as Motorola MC34064. The low voltagereset device MU6 is such that if the voltage on the input terminal INthereof, relative to ground, is below 4.5V, the reset output terminalRST produces a zero output voltage to ground; whereas, on the otherhand, if the voltage on the input terminal is above 4.5V, the resetoutput terminal RST produces approximately 4.5V to ground. Resistiveelement MR22 is a pull-down resistor element because device MU6 operatesin the open collector mode. Field effects transistor device MQ2 acts asan inverter producing a signal opposite to the one at the RST outputterminal of the device MU6. The voltage between the Drain and Source oftransistor MQ2 oscillates or changes between zero and 15V DC. The 15Voutput is determined by the zener diode device MCR6. Field effectstransistor device MQ3 acts as a series switch relative to the voltageproduced at the cathode of the diode MCR1, i.e., the voltage at point202A. The output voltage will be allowed to be imposed upon the sourceof field effects transistor MQ3 until a value of 24V is attained. Atthat point the action of the transistor MU6, MQ2 will cause theconduction path between the drain and the source of the field effectstransistor MQ3 to open. The voltage at the drain will dropinstantaneously to zero. This is shown as the voltage at point 203A inFIGS. 11C and 13. Diode MCR7 and capacitive element MC6 act as a filterso that the output voltage MVU at point 204A in FIGS. 11C and 13 isshown as a rather poorly regulated voltage MVU, which is approximately24V. It is necessary to regulate this latter voltage to produce thevalue MVDD, which is a highly regulated 5V DC value in this embodimentof the invention. In order to accomplish that, a 5V regulator device MU5is utilized. With the voltage wave shape MVU imposed on the "VIN"terminal of Device MU5, the output voltage at the "+5" terminal thereofis the highly regulated 5V DC value MVDD as shown.

The operation of the power supply circuit 202 is as follows. At thebeginning of the Region I, switch VSSM is on and diode MCR7 isconducting. The half wave rectified voltage is above zero but less than24V and is increasing towards 24V. Output voltage +MVU at 0.204A followsthe rectified voltage VREC shown in FIG. 13A which exists at 0.202A. Atthe end of Region I, the half wave rectified voltage VREC reaches 24Vand turns switch VSSM off. This immediately drops the voltage on theanode of the diode MCR7 to zero which causes that diode to ceaseconducting. During the period II, the switch VSSM is off and the diodeMCR7 is nonconducting. The voltage +MVU is determined by the dischargecharacteristic of the capacitor MC6 discharging through the remainder ofthe circuit connected to the power supply terminal +MVU. This continuesuntil the end of Region II, when the half wave rectifier voltage VRECshown in FIG. 13 drops below 24V. When this happens, switch VSSMimmediately turns on, however, the diode MCR7 remains in a nonconductingstate as the voltage on the anode thereof is less than the voltage onthe cathode thereof which is represented by the decay characteristic ofthe capacitor MC6 as was described previously. It will be noted that thevoltage on the anode of the diode decreases rapidly towards zero duringRegion III as it follows the wave shape VREC. The voltage on the cathodeof the diode MCR7 is also decreasing but not as fast as the voltage onthe anode. At the beginning of Region IV the capacitive elementcontinues its discharge because the switch VSSM though still in aconducting or on state allows voltage to be impressed on the anode ofthe diode MCR7 which is increasing but nevertheless still less than thedischarge voltage of the capacitor MC6. The end of Region IV is definedas that point where the increasing voltage VREC equals the decreasingvoltage of the capacitive element MC6 in which case the cycle beginsonce again. Note that once the output voltage approaches the switchcontrol voltage, the switch is automatically turned off, even if thevoltage sense circuit has not been activated. This has the advantage ofblocking the higher input voltages when charging and allowing thecircuit to continue to conduct if not fully charged. It also acts as aninternal phase angle controller.

Low voltage reset MU2, resistive element MR2, and capacitive elementMC13 produce the signal RESET for microprocessor MU3. In particular, aslong as the voltage across the resistive element MR2, which is connectedacross the IN-to-RST terminals of the device MU2, is above 4.5V, theRESET wave shape will be at 0V. However, if the latter-mentioned voltageacross the resistive element R2 drops below 4.5V, the RESET value willstep to a high value, which be sufficient to reset the microprocessorMU3. This will occur as a result of a voltage loss on the power supply202 which would cause the activity of the microprocessor MU3 to nolonger be considered reliable.

CALIBRATION TECHNIQUE

Referring now to FIGS. 10A-10C, 11A, 11B, 11D, 12, 14 and 15, theprocess for calculating a digital calibration factor for the electricaldevice 10 is described. In particular, the chip CU1 operating inconjunction with the remainder of the circuits of FIGS. 10, 11, sensesan electrical variable such as but not limited to an electrical currentIAIN by way of current sensors CL1A, CL1B, or CL1C, and provides thatcurrent to the chip CU1 by way of input terminals MUX0, MUX1, and MUX2,respectively. Sequentially, those input terminal are supplied byterminal MUX3 to an integrating capacitor or integrator CC6 forproducing a voltage representative of the currents in each case. Thatvoltage is then sequentially provided to an A/D converter throughterminal MX0 and thence to memory locations IA0, IA1, IB0, IB1, IC0,IC1, in the chip CU1 for phase currents A, B, C, respectively.

Key elements of the process include an adjustable current source PCS andproduct hardware including analog signal processing circuitry andsynchronous bidirectional serial communication link to an externalcomputer PC (product serves as "master" for link).

The procedure assumes that the product microprocessor CU1 utilizes again correction factor for each analog input which is used to adjust thedigitally processed values derived from the A/D converter output. Alsoit is assumed that for a time based calibration that the processor CU1utilizes a timer "tick" derived from a programmable timer. The timerconsists of a free running counter and an output compare register.Whenever a timer interrupt occurs, corresponding to the counter valueequalling the compare register contents, the register is reloaded withthe value required to produce the next equally spaced timer interrupt.The computation of this reload value involves a timer correction factorwhich can be used to adjust the time between timer interrupts. This canbe used to correct for oscillator variations due to the use of an RCoscillator rather than a crystal.

Referring to FIG. 12 specifically, it is recognized that for an idealsystem, the actual current sensed IAIN in this case should equal thecurrent as derived or interpreted by the chip CU1; IOUT in this case. Inan ideal situation a graph representing the relationship between IAINand IAOUT for equal scales on both ordinates should be a straight lineat a 45° angular offset from the horizontal axis; that merely says thatfor any particular value of input current IAIN chosen, the outputcurrent IAOUT or derived current utilized in the microprocessor CU1should be exactly the same. On the curve depicted in FIG. 12, that meansthat the angle j should be 45° and the offset OS should be zero.Therefore, the line designated AGC (assumed gain correction) shouldrepresent a slope of "1", which means that, as was stated previously,the input current will equal the output current. However, it is wellrecognized that the gain correction may not be ideal and, furthermore,offsets may exist. In this embodiment of the invention no correction ismade for the offset OS. However, correction is made for gain error. Thismeans that if, in actuality, the output current IAOUT does not equal theinput current IAIN but rather is related to the input current IAIN bythe straight line designated ACT (for actual current measurement), forexample, that a gain correction can be made, which ignores offset OS butwhich nevertheless places the corrected line COU at a relationship ofj=45° with respect to the horizontal axis of the graph of FIG. 12. Thiscorrected output utilizes the generation or calculation of digital gaincorrection factors in this embodiment of the invention.

In order to calculate gain correction factors for electrical current, aremote personal computer PC designated PC may be interconnected withterminal MP2 by way of a twisted pair of conductors TP. The remotepersonal computer PC may be interconnected by way of a CONI card ormodule. A precision current source PCS is utilized to provide precisionknown currents in the lines A, B, C, which are measured or monitored bythe current sensors CL1A, CL1B, CL1C, respectively. The precisioncurrents generated by the precision current source PCS are also madeavailable to the personal computer PC and is stored as a value in amemory portion thereof.

Referring now to FIG. 14, the flow chart designated thermal (THER) isprovided as part of the microprocessor control for the contactor ofFIGS. 10. For purposes of simplicity of illustration, the phasecorrection and calibration will be described only with respect to onecurrent which, in this embodiment of the invention, is arbitrarilychosen to be current IAIN. It is to be understood that correction andcalculation with respect to gain correction factors for other circuitvariables follow the same process. As indicated by block TH10, the firstoperation is to place the "pointer" of the microprocessor of the chipCU1 to a phase that has been uncorrected, which in this embodiment ofthe invention will be identified as the current contained in the 2-bytelocation IA0, IA1 for phase A. Each byte has eight bits of informationstored therein. This information represents a derived electrical value.According to block TH20, these two bytes of data are then placed by themicroprocessor portion of the chip CU1 into the TEMP0, TEMP1 randomaccess memory locations. According to block TH30, the microprocessorthen acquires corresponding correction constants such as ACAL from thecalibration factor memory region or EEPROM and places those correctionconstants or factors into memory locations TEMP2 and TEMP3. It isunderstood that how the correction constants are derived has not yetbeen fully explained, but will be explained in detail with respect toFIG. 14. In the equation Y=MX+B for the lines of FIG. 12, M representsthe slope or angle j for the various curves AGC, ACT, and COU. Theoffset OS as represented by the symbol B in the above equation isignored in this embodiment of the invention. The correction constantadjusts the slope 14. According to block TH40, the information stored inbytes TEMP0, TEMP1 is multiplied by the information stored in the bytesTEMP2, TEMP3 to produce the results I2RESULT. This is done by asubroutine designated "MUL2". The product of the multiplication isstored in the random access memory in locations I2RESULT0, I2RESULT1,I2RESULT2, and I2RESULT3, as indicated by block TH40. The product is a4-byte number. As is indicated in block TH50, it is necessary to correctfor the decimal point by rotating to the left the bytes I2RESULT 0, 1,2, 3 one time. This effectively places the decimal point in the correctplace. In essence it means to move the decimal point one binary place tothe left. And then, as indicated by block TH60, the I2RESULT 2, 3 bytesare placed back to where the phase current was found in the first place,which are locations IA0, IA1. This is equivalent of placing the mostsignificant digits of the I2RESULT information into memory. The newinformation in the locations IA0, IA1 now represents corrected orderived out current or the current designated IAOUT in FIG. 12. Thecorrection which has taken place has been one of slope correction ratherthan offset correction.

Referring now to FIG. 14 as well as FIGS. 10C, 11D, 12, the flow chartCALIBRATE for loading 2-byte gain correction information into locationsACAL, BCAL, and CCAL of the EEPROM of the chip CU1 is described. In thisembodiment of the invention and for purposes of simplicity, only thecalculation of the ACAL set of bytes is described. ACAL is a 2-byte,8-bit per byte, word. In order to arrive at the word, the personalcomputer PC downloads by way of the apparatus of FIGS. 10, 11 into thecontactor 10. The personal computer PC instructs the chip CU1 to placethe binary number 1.000000 into the ACAL location. This is a startingpoint, and this is depicted in calibrate flow chart CAL. The loading isspecifically depicted in block CAL10. The personal computer PC is thenutilized, as indicated at block CAL20, to start the contactor 10 in sucha manner that the contacts 22, 26, 44 and 46 thereof are closed, or atleast it appears to the chip CU1 that the contacts are closed. At thispoint, as indicated at block CAL30, a known precise current or a firstvalue of an input electrical variable is placed by way of the precisioncurrent source PCS through each of the three phases A, B, C of thecontactor 10, as the case may be, so that the sensing devices CL1A,CL1B, CL1C, operate in the manner previously described to sense theinput electrical variable (current) to thus place derived input currentinformation in the random access memory in locations IA0, IA1, IB0, IB1,IC0, IC1, respectively. According to block CAL40, the stored phase orderived currents are then read back or communicated to the personalcomputer PC in the manner described previously. According to blockCAL40, this may be done by a sampling technique in which phase currentsare sensed, stored, and read back to the personal computer PC a multiplenumber of times, which, in a preferred embodiment of the invention, maybe ten times, to provide an accumulated value of phase current in thepersonal computer, which is then divided by the number of entries, whichin this case is ten, to provide an average value of phase current. Thisis done according to block CAL50. At this point it is important torecognize that the calibration factor is "1", so that the data that hasbeen read back to personal computer PC is uncorrected data indicative ofwhat the entire system represented by FIGS. 10C, 10D interpret theprecision currents IA, IB, IC, to be. For instance, in a preferredembodiment of the invention, current IA, IB, IC may be 5-ampere rootmean square (RMS) current, and yet when read back to the programmablecontroller PC one may appear to be 4.997 amperes, indicating an error of0.003 ampere caused by error in the various elements shown in FIGS. 10C,10D. It is interesting to note at this point that the actual current,though being 5 amps, is derived by the system or interpreted thereby asbeing only 4.997 amps by the apparatus of FIGS. 10C, 10D. It is alsoimportant to recognize, and it is an important part of the presentinvention, that regardless of the value sensed by the personal computer,i.e., 4.997 amperes, the actual value being measured is 5 amperes, andtherefore the interpreted or derived value of 4.997 amperes reallyrepresent 5 amperes. The personal computer PC then takes these averagesamples and compares them against the known expected value, which is 5amperes. The personal computer PC then calculates the calibration factoraccording to the relationship: the calibration factor equals the firstvalue of input electrical current divided by the first derived value.For example, in the personal computer PC the expected or first value of5 amperes is divided by the actual or derived value of 4.997 to producea correction constant 1.006; this is done according to block CAL60.Blocks CAL70, CAL80 digitally manipulate the data to place it in aproper form for being resubmitted or communicated to the calibrationfactor memory of the chip CU1 for digital placement therein. Block CAL90indicates that the correction constant should be downloaded into thecorresponding locations in the contactor EEPROM memory. This is a memorywhich is nonvolatile, and once values are stored or "locked" thereinthey cannot be easily removed. Consequently, once the device in questionhas been calibrated at the factory and the proper calibration valueshave been loaded into the EEPROM memory, the customer/user cannotinadvertently erase the valuable calibration data. This information isstored in the ACAL, BCAL, CCAL locations in the EEPROM memory. As isshown in block CAL95, the personal computer PC interrogates the EEPROMto verify that the values which were downloaded are correct. At thispoint the calibration procedure has been completed. It will be noted byreferring again to FIG. 14, block TH30, that when the chip CU1 isinstructed to acquire the corresponding correction constants and placethem in RAM locations TEMP2,3, for example, it is the correctedcalibration values ACAL, BCAL and CCAL which are placed into the TEMP2,3locations. Consequently, when device 10 performs its useful function,the appropriate derived value will be effected by the calibrationfactor.

Referring once again to FIGS. 10, 11, the path of communication betweenthe personal computer PC and the memories of the chip CU1 is described.In particular, information travels from the personal computer PC to thememories of the sure chip CU1 in the following manner: Informationtravels down the twisted pair TP to the connector MP2 in the form ofzeroes and ones represented by modulated high frequency AC signals fromwhence the information is provided by way of the transformer MT1 to thedemodulator represented by the circuitry associated with the comparatorMU1A, to then be provided as a series of digital ones and zeroes at theoutput terminal MRX. The output terminal MRX is interconnected with thebasic INCOM chip MU4 from whence it is supplied by way of the serialdata channel SERDAT to terminal PA2 of the microprocessor MU3, and fromthence to the data OUT line DO to the connector MJ2 at terminal 5. Therethe data goes to the connector CJ2 at terminal 4 and the DI line. Fromthence the data moves to the SDI terminal of the chip CU1 where it maybe routed to an EEPROM location therein.

Data such as ACAL resident in the EEPROM of the chip CU1 may betransferred out by way of the SDO terminal of the surechip CU1 and theDO output line to the connector CJ2 at terminal 5. From there the datais routed to the connector MJ2 at terminal 6 and to the DI input lineand thence to the MISO input terminal of the microprocessor MU3. Fromthere it is provided from terminal PA2 to the SERDAT terminal of theINCOM chip MU4, and from there to the TX output terminal as signal MTX.The TX output terminal feeds the modulator circuit represented, forexample, by the comparator MU1B and the field effect transistor MQ1, asshown in FIG. 11D. From there the data is fed by way of the resistorMR14 to the secondary winding MS1 of the transformer MT1, and then backthrough connector MP2 and the twisted pair TP and to the personalcomputer.

Amplitude Calibration Method 1

This procedure utilizes the product microprocessor MU3 to calculate thegain correction factor based on a digital message received from theexternal computer PC that the test currents are at the desiredcalibration values. In this case the external computer PC could even bereplaced by a jumper to other parts of the chip CU1 or themicroprocessor MU3 which will cause the product to execute thecalibration code, calculate the gain constants, and store the values innonvolatile memory.

This technique has the advantage that it is simple, reliable and doesnot require an external computer.

Amplitude Calibration Method 2

In this procedure the gain factor calculation is done by the externalcomputer PC as described previously. The product through thecommunications channel passes to the external computer PC both the valueof currents and the associated gain factors which the product used tocalculate the current values. The external computer PC compares thecurrent values received from the product to those received from thecurrent transducers. New gain factors are then calculated and sent tothe chip CU1 for storage in nonvolatile memory as shown below:

    GAIN FACTOR new=GAIN FACTOR old * (CURRENT from the reference/CURRENT from the product)

Time Calibration Method 1

The oscillator frequency can be measured directly by means of afrequency meter. The external computer PC can calculate the timercompare register load value increment by

    LOAD VALUE new=LOAD VALUE ideal * (OSC.FREQ. actual/OSC.FREQ. ideal)

This value can be sent to product for storage in nonvolatile memory.

Time Calibration Method 2

A more automatic method for time calibration uses circuitry associatedwith the external computer PC to measure the frequency of the serialclock or some other product microprocessor output which is related tothe product's execution time and then automatically sends a request tothe product to either increase or decrease compare the register loadincrement.

Referring now to Table I, the pin reconciliation for the input pins ofthe INCOM chip MU4 of the present specification and the INCOM chip ofthe incorporated-by-reference U.S. Pat. No. 4,644,547 is set forth.

                  TABLE I                                                         ______________________________________                                        PIN RECONCILIATION                                                            Pin Numbers  Pin Numbers                                                      This INCOM   INCOM Chip of                                                    Chip (MU4)   U.S. Patent 4,644,547                                            ______________________________________                                        1            28                                                               4            4                                                                5            3                                                                6            5                                                                7            6                                                                9            8                                                                10           9                                                                11           10                                                               12           11                                                               13           12                                                               14           13                                                               15           14                                                               16           15                                                               17           16                                                               18           17                                                               19           18                                                               20           19                                                               21           20                                                               22           21                                                               23           22                                                               24           23                                                               25           24                                                               26           25                                                               27           26                                                               ______________________________________                                    

Ultrasonic Coil Current Regulator

An important aspect of the invention relates to an ultrasonic coilcurrent regulator. As previously mentioned, phase angle currentregulator circuits, for example, as disclosed in U.S. Pat. No. 4,893,102can cause audible noise in the electromagnet assembly. This noise isgenerated as a result of the relatively high rate of change of fluxdeveloped within the solenoid coil SC in response to the abrupt changesin the electrical current pulses, for example, as shown in FIG. 6 of theaforementioned patent applied to the solenoid coil SC during thiscondition. An important aspect of the invention relates to the fact thata regulated source of electrical current is applied to the solenoid coilduring both the closing and hold in condition. The regulated source ofelectrical current eliminates abrupt changes in the magnitude ofelectrical currents applied to the solenoid coil SC which, in turn,reduces the rate of change of flux therethrough which eliminates audiblenoise from the electromagnet assembly. Moreover, by supplying aregulated source of electrical current to the solenoid coil, the RMSvalue of the electrical current applied during the hold in conditionwill be relatively less than the RMS current value in a phase angleregulated circuit as described in the aforementioned U.S. patent. Morespecifically, in a phase angle regulated circuit, the force required toopen the contacts is determined by the lowest decay point of theelectric current supplied to the solenoid coil SC between updates. Sincethe updates in that circuit are so far apart, it is necessary to supplya relatively higher RMS electrical current to prevent the biasingsprings from causing the main contacts to open. This relatively higherRMS current provides additional heating of the solenoid coil SC. Thisproblem is solved by the present invention by providing a regulatedsource of electrical current to the solenoid coil SC during a hold incondition.

The circuit in accordance with the present invention provides anelectrical current profile to the solenoid coil SC as shown greatlyexaggerated in FIG. 10D. Since the circuit prevents the electricalcurrent from decaying to a relatively low value, such as in theaforementioned U.S. patent, the circuitry is able to automaticallycompensate for magnetic coupling from the main poles which otherwisecould cause the contactor to open. Consequently, a relatively high holdin force is also provided which allows relatively lower input voltagesthan previously possible. Moreover, the circuitry provides relativelyfast on to off time, which allows the off time to be fairly large whilealso minimizing amplitude changes in the output current which minimizesenergy consumption of the coil which, in turn, reduces undesirable coilheating.

With reference to FIGS. 10E-10H, the circuitry in accordance with thepresent invention includes a pair of power switches generally identifiedwith the reference numerals UCR-1 and UCR-2, for connecting the solenoidcoil SC to a source of electrical power. The power switches UCR-1 andUCR-2 are under the control of a power drive circuit UCR-5, a triggercircuit, identified with the reference numeral UCR-3 and a timingcircuit, identified with the reference numeral UCR-4. As will bedescribed in more detail below, on power-up, the power drive circuitUCR-5 is under the control of the timing circuit UCR-4. Morespecifically, during power-up, the timing circuit UCR-4 controls thepower drive circuit UCR-5 such that the power switches UCR-1 and UCR-2close to connect the solenoid coil SC to a source of electrical power,for example, a full wave rectified unfiltered source of electricalpower. Once the power switches UCR-1 and UCR-2 close, the electricalcurrent in the solenoid coil SC is monitored. When the electricalcurrent reaches a predetermined level, the trigger circuit UCR-3triggers the timing circuit UCR-4 to disable the power drive circuitUCR-5 for a predetermined time period causing the power switches UCR-1and UCR-2 to open, thus disconnecting the solenoid coil SC relativelyquickly from the source of electrical power for such time period. Duringthe predetermined time period, the electrical current in the solenoidcoil SC is allowed to decay. The relatively quick disconnection of thesolenoid coil SC from the source of electrical power allows the energyapplied to the solenoid coil to be reduced, which, in turn, reducesundesirable heating in the solenoid coil SC. After the predeterminedtime period times out, the timing circuit UCR-4 triggers the power drivecircuit UCR-5 to cause the power switches UCR-1 and UCR-2 to close,which, in turn, connects the solenoid coil SC to the source ofelectrical power. The cycle is then repeated.

Two embodiments of the invention are disclosed. In a first embodiment ofthe invention, the trigger circuit UCR-3 includes a feedback circuitillustrated in FIG. 10F for comparing the electrical current in thesolenoid coil SC with a reference value. More specifically, in bothembodiments, a current sensing resistor is provided to convert theelectrical current flowing in the solenoid coil SC to a representativevoltage. This representative voltage is then compared with a referencevoltage by way of a comparator to provide a trigger signal to the timingcircuit UCR-4 when the representative voltage equals or exceeds thereference voltage. In the second embodiment of the invention,illustrated in FIG. 10H, the feedback circuit is substituted with abipolar transistor. In this embodiment, the representative voltage isapplied across a base-emitter junction of a bipolar transistor.

In both embodiments of the invention, the power switch and drivecircuitry illustrated in FIG. 10b, which includes the resistors CR14through CR18, CR26, the optocoupler CU2, the transistor CQ3 and CQ4 aswell as the diode CCR4, is substituted with the circuitry illustrated inFIGS. 10E, 10F and 10G. The balance of the circuitry heretoforedescribed illustrated in FIGS. 10A, 10B, 10C, 11A, 11B and 11C isessentially the same as heretofore described. In these embodiments, thesolenoid coil SC is connected to terminals 1 and 2 of a terminal blockCJ4 (FIG. 10E). As previously discussed, a source of AC control power,for example 120 volts AC, is applied to terminals 3 and 4 of theterminal block CJ1 (FIG. 10A). The control power is, in turn, applied toa full wave rectifier which includes diodes CD6, CD7, CD8 and CD9. Thefull wave rectifier defines a positive DC terminal identified as "E" anda negative DC terminal which is applied to the SURE CHIP integratedcircuit CU1 (described in U.S. Pat. No. 5,325,315) in a manner asdiscussed above. The negative DC terminal is also connected to ground byway of a resistor CR17 as discussed above. The full wave rectifierprovides full wave unfiltered voltage to the solenoid coil SC. Morespecifically, the full wave rectifier defines a pair of terminalsidentified in FIG. 10G as "+VDC" and "DC". As shown in FIG. 10E, the+VDC terminal is applied to terminal 1 of the terminal block CJ4 whilethe DC terminal is connected to the current sensing circuitry (FIG.10F).

The balance of the circuitry illustrated in FIG. 10G relates to aregulated power supply for generating a DC voltage identified as +V.This circuitry includes transistors CQ13, CQ14, Zener diodes CZ3 andCZ4, a diode CD12, capacitors CC15 and CC20 and resistors CR26, CR49,CR51, CR54, CR57, CR86 and CR95. In operation, the unfiltered, rectifiedvoltage +VDC is applied across the resistors CR54 and CR57 which, inturn, causes the transistor CQ14 to turn on. The capacitor CC20 disposedin parallel with the resistors CR54 and CR57, prevents any rapid changesin +VDC. Once the transistor CQ14 is turned on, this causes thecollector to go low due to the voltage drop across the resistors CR26and CR51, which, in turn, gates the transistor CQ13. Once the transistorCQ13 turns on, electrical current through the resistor CR95 generatesthe voltage +V. The diode CD12, disposed in parallel with the resistorCR95, provides voltage clipping. The Zener diodes CZ3 and CZ4 as well asthe resistor CR86 is for protection of the transistors CQ13 and CQ14.

Referring to FIG. 10E and 10F, the first embodiment of the ultrasoniccoil current regulator in accordance with the present invention isillustrated. The control circuit in accordance with the presentinvention includes the power switch, disposed within the dashed boxidentified as UCR-1, which includes the field effect transistors CQ6 andCQ7, arranged such that their respective drain and source terminals areconnected in parallel. One end of the parallel connected transistors CQ6and CQ7 is connected to one end of the solenoid coil SC by way of theterminal block CJ4. The other end of the transistors CQ6 and CQ7 isattached to another power switch, disposed within the dashed boxidentified as UCR-2, which includes a pair of parallel coupledtransistors CQ16 and CQ17. The power switch UCR-2, in turn, is connectedto a flyback diode CD10 which, in turn, is connected to the other sideof the solenoid coil SC by way of the terminal block CJ4.

The power switches UCR-1 and UCR-2 are utilized to connect the solenoidcoil SC to the current regulator circuit in order to regulate theelectrical current that flows therethrough. More specifically, a currentsensing resistor CR67 is serially connected to the solenoid coil SC byway of the power switches UCR-1 and UCR-2. Thus, any electrical currentthat flows through the solenoid coil SC is sensed by the current sensingresistor CR67 to develop a voltage proportional to the magnitude ofelectrical current flow through the solenoid coil SC. This voltage isapplied to a trigger circuit, illustrated within the dashed boxidentified as UCR-3, by way of a voltage divider circuit which includesa plurality resistors CR12 and CR66. In the first embodiment, thetrigger circuit UCR-3 includes a plurality of transistors CQ11 and CQ12,a plurality of resistors CR14, CR15, CR16, CR63, CR64, CR65, CR75 andCR79, a plurality of capacitors CC9, CC16 and CC17, a diode CD11, anoptocoupler CU5 and an operational amplifier CU4. The trigger circuitUCR-3 is used to control a timing circuit illustrated within the dashedbox identified as UCR-4. The timing circuit UCR-4 includes a monostablemultivibrator CU6, an optocoupler CU2, a plurality of resistors CR18,CR60, CR61, CR80 and CR91, a capacitor CC8 and a transistor CQ10. Thetiming circuit UCR-4 is used to control the power drive circuit shownwithin the dashed box UCR-5 for controlling the switching of the powerswitches UCR-1 and UCR-2. The power drive circuit UCR-5 includes aplurality of transistors CQ8, CQ9, CQ15 and CQ17, a plurality ofresistors CR55, CR68, CR69, CR70, CR81, CR83, CR84, CR93, CR96, CR98 andCR99, a capacitor CC19, a plurality of Zener diode Z5, Z6, Z7, Z8 andZ10 and a diode D13. The power drive circuit UCR-5 functions to controlthe switching of the power switches UCR-1 and UCR-2 in response to thetiming circuit UCR-4 as well as the trigger circuit UCR-3 in order toregulate the electrical current flowing through the solenoid coil SC asdescribed below.

Two control signals from the SURE CHIP integrated circuit CU1 (describedin U.S. Pat. No. 5,325,315) control the operation of the ultrasonic coilregulator circuit in accordance with the present invention. Thesecontrol signals are identified as "TIMEOPEN" and "FETDRIVE", availableat terminals PC2 and PC5 of the SURE CHIP integrated circuit CU1 (FIG.10A), respectively. These signals FETDRIVE and TIMEOPEN do not form apart of the present invention and are described hereinbelow to theextent necessary to understand the present invention. In general, theFETDRIVE signal is a series of pulses, generated to control the velocityof closing of the contactor in a manner similar as described in detailin U.S. Pat. No. 4,893,102, assigned to the same assignee as the presentinvention and hereby incorporated by reference. The TIMEOPEN signal isused to control the current regulator. Both the FETDRIVE and TIMEOPENsignals, are utilized in conjunction with the trigger circuit UCR-3 tocontrol the closing of the contactor. More specifically, once a startrequest has been received, for example, a contact closure is sensedbetween the terminals 1 and 4 of the terminal block CJ1 (FIG. 10A) and apermissive signal "P" is available as described above, both the TIMEOPENsignal as well as the FETDRIVE signal go high. The FETDRIVE signal isapplied to the optocoupler CU5, which forms a part of the triggercircuit, UCR-3 by way of the resistor CR75. This, in turn, activates anoutput transistor within the optocoupler CU5 in order to apply a voltageto the gate of the transistor CQ12. More specifically, once the input ofthe optocoupler CU5 is activated, the output transistor is biased on bythe resistors CR63 and CR73. This causes the transistor CQ12, whose gateis connected to the output transistor, to transition from a lowimpedance state to a high impedance state. This allows the transistorCQ12 to form a voltage divider with the resistor CR64 in order toprovide a sufficient gate voltage to the transistor CQ11.

The transistor CQ11 controls the current regulation of the circuit. Morespecifically, when the transistor CQ11 is on, the voltage applied to thenegative terminal of the operational amplifier CU4 will be held belowthe reference value to disable the timing circuit UCR-4. This allows forthe normal closing current to flow through the solenoid coil SC. Thenormal closing current is relatively larger, for example, ten times,then the value of the regulated current applied to the solenoid coil SCduring a hold in operation in order to maintain the separable maincontacts in a closed position. Once the closing profiles are complete,the FETDRIVE signal goes low. As will be discussed in more detail below,the contactor will remain in a closed position until the TIMEOPEN signalgoes low.

The TIMEOPEN signal is applied to the optocoupler CU2, which forms apart of the timing circuit UCR-4, by way of the resistor CR91. Theresistor CR91 is used to limit the electrical current to the lightemitting diode forming the input to the optocoupler CU2. This, in turn,activates an output transistor in the optocoupler CU2. A resistor CR80is connected between the base and emitter terminals of the outputtransistor in the optocoupler CU2 for biasing. The collector terminal ofthe output transistor within the optocoupler CU2 is connected to a baseterminal of the transistor CQ10. The transistor CQ10, connected to theoutput transistor of the optocoupler CU2, is normally on (e.g., when theTIMEOPEN signal is low) by way of the resistor CR60 connected betweenthe base thereof and the voltage +V generated by the power supplydiscussed above. However, since the collector terminal of the outputtransistor in the optocoupler CU2 is serially connected to the baseterminal of the transistor CQ10, once the output transistor of theoptocoupler CU2 is turned on, this action clamps off the transistorCQ10. Since the collector and emitter terminals of the transistor CQ10are connected in parallel with the capacitor CC8 by way of the resistorCR18, once the transistor CQ10 is turned off, the capacitor CC8 ischarged by way of the serially coupled resistor CR61. Once the voltageacross the capacitor CC8 exceeds a predetermined value, for example,two-thirds the value of +V, the output of the monostable multivibratorCU6, which may be, for example, a Motorola MC14528B, transitions. Morespecifically, one end of the capacitor CC8 is applied to a triggerterminal Al within the monostable multivibrator CU6. Once the capacitorCC8 charges to a predetermined voltage level, the Q1 output of themonostable multivibrator CU6 will go high. This causes the transistorCQ9 to turn on. When CQ9 turns on, a voltage is applied to the gates ofthe power switch transistors CQ16 and CQ17. This voltage causes thetransistors CQ16 and CQ17 to turn on. As will be discussed in detailbelow, this also causes the power switch transistors CQ6 and CQ7 to turnon, which, in turn, allows electrical current to flow through thesolenoid coil SC.

This electrical current also flows through the current sensing resistorCR67 where it is converted to a voltage. The voltage developed acrossthe resistor CR67 is applied to an inverting input of the operationalamplifier CU4 by way of a voltage divider which includes the resistorsCR12 and CR66. This voltage, which represents the electrical currentflow through the solenoid coil SC, is compared with a reference voltage,derived from the voltage V+ by way of the resistors CR14, CR15 and CR16.The reference voltage is applied to the non-inverting input of theoperational amplifier CU4. Once the electrical current flowing throughthe solenoid coil SC builds up to a value which causes a voltage acrossthe resistor CR67 to be greater than the reference voltage at theoperational amplifier CU4, the operational amplifier CU4 transitions andresets the monostable multivibrator CU6. The output of the comparatorCU4 is applied to the trigger input B1 of the monostable multivibratorCU6 which causes the power switches UCR-1 and UCR-2 to disconnect thesolenoid coil SC from the circuit for a predetermined time period aswill be discussed below.

The electrical current through the solenoid coil SC also passes throughthe resistor CR17 (FIG. 10G). The resistor CR17 is used to convert theelectrical current to a voltage which can be read by the SURE CHIPintegrated circuit CU1 for selecting the proper closing profile.

Once the contactor is closed, the FETDRIVE signal goes low and theseparable main contacts will remain closed until the TIMEOPEN signalgoes low. During this condition a hold in current is applied to thesolenoid coil SC to prevent the contactor from opening under theinfluence of the biasing springs.

The regulation of the electrical current through the solenoid coil SCafter the contactor is closed (e.g., hold in current) is controlled bythe timing circuit UCR-5. More specifically, as the voltage across thecapacitor CC8 exceeds a predetermined value, for example, two-thirds ofthe magnitude of the voltage +V, the output of the monostablemultivibrator CU6 goes low. This, in turn, turns on the P channeltransistor CQ9. The P channel transistor CQ9, in turn, turns on thepower switching transistors CQ16 and CQ17 which, as will be describedbelow turns on the transistors CQ6 and CQ7. This allows electricalcurrent to flow through the solenoid coil SC and be sensed by thecurrent sensing resistor CR67. The voltage developed across the sensingresistor CR67 is applied to the comparator CU4 by way of the voltagedivider formed from the resistors CR12 and CR66. When the electricalcurrent through the solenoid coil SC exceeds a predetermined value, thevoltage applied to the comparator CU4 will exceed the reference voltageand cause the comparator CU4 to go low. As previously mentioned, sincethe output of the comparator CU4 is connected to the trigger input B1 ofthe monostable multivibrator CU6, this low causes the output of themonostable multivibrator CU6 to transition from high to low. This, inturn, allows the capacitor CC8 to be discharged to approximatelyone-third of V+ which, in turn, causes the Q1 output of the monostablemultivibrator CU6 to go high. This, in turn, causes the transistor Q9 toturn off and the transistor Q8 to turn on. Once this occurs, this causesthe transistors Q16 and Q17 as well as the transistors CQ6 and CQ7 toturn off. During this off time, the capacitor CC8 charges to apredetermined value, for example, two-thirds +V. Once the voltage acrossthe capacitor CC8 reaches this value, the Q1 output of the monostablemultivibrator CU6 will go high and the cycle will be repeated. Thecircuitry thus allows the transistors CQ16 and CQ17 to be cycled at anaturally varying frequency.

As discussed above, the state of the transistors CQ6 and CQ7 iscontrolled by the state of the transistors CQ16 and CQ17. Morespecifically, whenever the switching transistors CQ16 and CQ17 turn on,the parallel connected resistors CR55 and CR84 pass electrical currentthrough the Zener diode CZ8. The voltage reference, formed at the Zenerdiode CZ8, forms an emitter follower with the transistor CQ15. Theoutput of the transistor CQ15 is connected to a diode CD13 which, inturn, is used to charge a serially coupled capacitor CC19. The voltageacross the capacitor CC19 is applied to the gate of the transistors CQ6and CQ7. Thus, whenever the power transistors CQ17 and CQ16 turn on, thetransistors CQ7 and CQ6 will also be on. Whenever the transistor CQ17turns off, the capacitor C19 discharges through the resistor C83. Thisdecay is usually short in duration because the transistor CQ17 turns on,for example, every 100 microseconds.

As previously mentioned, the circuit will maintain a sufficientregulated holding current relative to the solenoid coil SC until theTIMEOPEN signal is removed (e.g., goes low). More specifically, when theTIMEOPEN signal goes low, the transistors CQ17 and CQ16 turn off,thereby opening the electrical current path to the solenoid coil SC.After the transistors Q16 and Q17 are turned off, the voltage across thecapacitor C19 begins to decay. The values of the capacitor CC19 as wellas the discharge resistor CR83 are selected such that the FET gatethreshold is not reached until a predetermined value, for example,approximately three-quarters of the holding energy remains in thesolenoid coil SC.

As the transistors CQ6 and CQ7 begin to turn off, a voltage buildsthereacross which is applied to the base of the transistor CQ18 by wayof the resistor R97. When the transistor CQ18 turns on, the decay rateis increased since the resistor CR98 is now in parallel with theresistor CR83. This forces the transistors CQ6 and CQ7 to turn offwhich, in turn, separates the solenoid coil SC from the flyback diodeCD10. The resistor CR83 holds the transistors CQ6 and CQ7 off until thenext time the transistors CQ16 and CQ17 are permitted to turn on.

In an alternate embodiment of the invention the trigger circuit UCR-3,connected between the terminals identified as T1, T2 and T3 (FIG. 10F),is substituted with the circuit illustrated in FIG. 10g which includes atransistor CCQ2 and a resistor CCR10. More specifically, the emitterterminal of the transistor CCQ2 is connected to terminal T3 while thebase terminal is connected to terminal T1. The collector terminal isconnected to terminal T2. The power supply voltage +V is connected tothe collector by way of the resistor CCR10.

In this embodiment, the collector voltage of the transistor CCQ2 is usedto trigger the monostable multivibrator CU6 instead of the feedbackcircuit. More specifically, as previously described, the FETDRIVE andTIMEOPEN signals are used to control switching of the transistors CQ6,CQ7, CQ16 and CQ17 in a manner as discussed above. Once thesetransistors CQ6, CQ7, CQ16 and CQ17 are turned on, electrical currentflows through the solenoid coil SC which is sensed by the currentsensing resistor CR67. The voltage across the current sensing resistorCR67 is applied to the base of the transistor CC12 by way of the voltagedivider formed from the resistors CR12 and CR66. When the transistorCCQ2 turns on, the voltage at the collector terminal drops. Thecollector terminal of the transistor CCQ2 is connected to the triggerinput B1 of the monostable multivibrator CU6 to cause the Q output to gohigh. This action causes the transistors CQ6, CQ7, CQ16 and CQ17 to turnoff for a fixed period of time as determined by the resistor CR61 andthe capacitor CC8 as discussed above. Once the fixed time period timesout, the Q output of the monostable multivibrator CU6 goes low to turnon the transistors CQ6, CQ7, CQ16 and CQ17 in a manner as describedabove and the cycle is repeated.

Column 4, line 39 through column 6, line 45; column 26, line 53 throughcolumn 90, line 25; and FIGS. 16-18, 19A-19D, 20-32, 33A-33D and 34-68of U.S. Pat. No. 5,325,315 are incorporated by reference herein.

Many modifications and variations of the present invention are possiblein light of the above teachings. Thus, it is to be understood that,within the scope of the appended claims, the invention may be practicedotherwise than as specifically described above.

What is claimed and desired to be secured by Letters Patent of theUnited States is:
 1. An electrical device for connecting a source ofelectrical power to an electrical load comprising:one or more pairs ofseparable main contacts; an electromagnet including an armaturemechanically interlocked with said one or more pairs of separable maincontacts, said armature movably mounted to allow said one or more pairsof separable main contacts to be placed in a CLOSED position oralternatively in an OPEN position, said electromagnet also including asolenoid coil for controlling the movement of said armature; means forconnecting said solenoid coil to a source of electrical power in orderto apply electrical current to said solenoid coil; means for sensing theelectrical current applied to said solenoid coil; means for modulatingthe sensed electrical current of said sensing means; means for comparingthe modulated sensed electrical current of said modulating means with apredetermined value; and regulating means cooperating with saidcomparing means for regulating the electrical current applied to saidsolenoid coil, said modulating means modulating the sensed electricalcurrent of said sensing means in order to place said separable maincontacts in the CLOSED position from the OPEN position, said regulatingmeans for regulating the electrical current applied to said solenoidcoil in order to maintain said separable main contacts in the CLOSEDposition.
 2. The electrical device as recited in claim 1, wherein saidsensing means includes resistor means serially coupled to said solenoidcoil; and wherein said modulating means includes dividing means andswitching means, the dividing means parallel coupled to the resistormeans and having a tap, the switching means connected to the center tapof the dividing means.
 3. The electrical device as recited in claim 2,wherein the resistor means includes a first resistor serially coupled tosaid solenoid coil, the first resistor having two nodes; and wherein thedividing means includes a second resistor connected between a first nodeof the first resistor and the tap of the dividing means, and a thirdresistor connected between the tap of the dividing means and a secondnode of the first resistor.
 4. The electrical device as recited in claim1, wherein the source of electrical power is an alternating currentpower source; wherein said connecting means includes full wave rectifiermeans for rectifying the alternating current power source; wherein theelectrical current applied to said solenoid coil is a full waverectified electrical current; and wherein the sensed electrical currentof said sensing means is derived from said full wave rectifiedelectrical current.
 5. The electrical device as recited in claim 1,wherein said regulating means includes means responsive to saidcomparing means for disabling said regulating means for a predeterminedtime period when said electrical current applied to said solenoid coilreaches a predetermined value; and wherein said comparing means includesmeans for providing a trigger signal directly to the disabling means. 6.The electrical device as recited in claim 5, wherein the trigger signalproviding means provides the trigger signal when said electrical currentapplied to said solenoid coil reaches a predetermined value.
 7. Theelectrical device as recited in claim 5, wherein the disabling meansincludes means for providing a timing signal responsive to the triggersignal; and wherein said timing signal providing means includes amonostable multivibrator, directly responsive to said comparing means.8. An electrical device as recited in claim 1, wherein said comparingmeans includes an operational amplifier.
 9. The electrical device asrecited in claim 1, wherein said regulating means includes meansresponsive to said comparing means for disabling said regulating meansfor a predetermined time period when said electrical current applied tosaid solenoid coil reaches a predetermined value; and wherein saidcomparing means includes a transistor and means for biasing saidtransistor as a function of said electrical current applied to saidsolenoid coil, the transistor providing a trigger signal directly to thedisabling means.
 10. An electrical device for connecting a source ofelectrical power to an electrical load comprising:separable contactmeans; electromagnet means including an armature mechanicallyinterlocked with said separable contact means, said armature movablymounted to allow said separable contact means to be placed in a CLOSEDposition or alternatively in an OPEN position, said electromagnet meansalso including a solenoid coil for controlling the movement of saidarmature; means for connecting said solenoid coil to a source ofelectrical power in order to apply electrical current to said solenoidcoil; means for sensing the electrical current applied to said solenoidcoil; modulating means for modulating the sensed electrical current ofsaid sensing means, said modulating means having a first stateassociated with the OPEN position of said separable contact means, asecond state associated with placing said separable contact means in theCLOSED position from the OPEN position, and a third state associatedwith the CLOSED position of said separable contact means; trigger signalproviding means cooperating with said modulating means for providing atrigger signal when the modulated sensed electrical current of saidmodulating means reaches a predetermined value; and regulating meanscooperating with said trigger signal providing means for regulating theelectrical current applied to said solenoid coil in order to maintainsaid separable contact means in the CLOSED position.
 11. The electricaldevice as recited in claim 10, wherein said modulating means includes atransistor having a first static state, a second static state associatedwith the CLOSED position of said separable contact means, and a dynamicstate associated with placing said separable contact means in the CLOSEDposition from the OPEN position, the dynamic state including a series oftransitions between the first and second static states.
 12. Theelectrical device as recited in claim 11, wherein said sensing meansincludes resistor means serially coupled to said solenoid coil; andwherein said modulating means further includes dividing means parallelcoupled to the resistor means and having a tap, the transistor connectedto the tap of the dividing means.
 13. The electrical device as recitedin claim 11, wherein the transistor is turned on during the first staticstate thereof and is turned off during the second static state thereof.14. The electrical device as recited in claim 10, wherein saidregulating means includes means responsive to said trigger signalproviding means for disabling said regulating means for a predeterminedtime period when said electrical current applied to said solenoid coilreaches a predetermined value.